1. Field of the Invention
The present invention relates in general to a process for fabricating an MOS transistor, and more particularly to improvement in a short channel effect and a hot carrier effect and a threshold voltage in the MOS transistor.
2. Description of the Prior Art
In a conventional p type MOS transistor, at edge portions of a gate electrode occurs a high electric field, which forces hot carriers to be generated. The generated hot carriers are often trapped in a gate insulating film in the transistor, causing a charge trap or interface state to occur in the insulating gate. These hot carriers serve to degrade an operation characteristic of a p type MOS transistor fabricated and reduce the use life expectancy thereof.
In an effort to curtail the hot carrier effect, a p type MOS transistor having a lightly doped drain (hereinafter "LDD") structure has been proposed. This p type MOS transistor of LDD structure will be explained by referring to FIG. 1 for better understanding of the background of the invention. There is shown a step diagram for the conventional process flow of the p type MOS transistor of LDD structure.
As shown in FIG. 1, in step A, a gate oxide film 13 is formed over an n type semiconductor substrate 11. A p.sup.+ type polycrystalline silicon (polysilicon) film doped with p type impurity ions is entirely formed on the gate oxide film 13 and is then subjected to a patterning so as to form a gate 15. Using the gate 15 as a mask, p type impurity ions such as B ions and BF.sub.2 ions are implanted at such a low density as to form source/drain regions having a low p.sup.- density.
Subsequently, in step B, the fabrication of the p type MOS transistor of LDD structure is finished. For this, firstly, an oxide film is deposited entirely on the substrate and is then subjected to the treatment of anisotropic etching so as to form spacers 19 at side sites of the gate 15, leaving them shaped into side walls, respectively, as shown in the figure. Next, using the spacers 19 and the gate 15 as a mask, p type impurity ions such as B ions or BF.sub.2 ions are implanted in the substrate 11 at such a high density as to form source/drain regions 21 having a high p.sup.+ density.
In the above MOS transistor of LDD structure, the drain region 17 having a low p.sup.- density allows the high electric field applied to the drain region to become lowered, so that the degradation of operation characteristics in the device caused by the hot carriers can be prevented, thereby improving the reliability of the device.
In case of fabricating a very small LDD MOS transistor for a device having a storage capacity of 256M or more, the p.sup.- source/drain regions which have a function of eliminating the hot carrier effect must have a shallow junction depth, for example, several hundreds .ANG. such that a short channel effect is not affected.
However, the conventional process utilizing ion implantation method finds difficulty in producing an LDD MOS transistor having a storage capacity of 256M or more. Hereinafter, this problem will be briefly discussed for better understanding. As mentioned above, as a p type impurity used for forming p type source/drain regions, B or BF.sub.2 is employed. Since boron (B) ions have so great diffusivity, the low density p.sup.- source/drain regions having a shallow junction are hard to form by the application of ion implantation process. Accordingly, the short channel effect of the device is reversely affected.